DIVIDE BY 3 COUNTER

11:53 AM     

module div_by_3(clk,reset,clk_3);
input    clk      ;
input    reset    ;
output   clk_3    ;

wire       Da     ;
reg        Qa     ;
reg        Qb     ;
reg        Qc     ;

  assign Da   =~Qa && ~Qb  ;
  assign clk_3= Qb ||  Qc  ;

  always@(posedge clk or negedge reset ) begin
    if(~reset)begin
     Qa<=1'b0 ;
    end
    else begin
     Qa<=Da   ;
    end
  end

  always@(posedge clk or negedge reset ) begin
    if(~reset)begin
     Qb<=1'b0 ;
    end
    else begin
     Qb<=Qa   ;
    end
  end
  
  always@(negedge clk or negedge reset ) begin
    if(~reset)begin
     Qc<=1'b0 ;
    end
     else begin
     Qc<=Qb   ;
    end
  end
endmodule