String tasks in verilog

Note : If you are planning to use these Tasks with SystemVerilog then Please change byte to byte1 & char to char1 because both are keywords in system verilog .

Calculate the length(length) of string(str) in verilog .


Usage : strlen(str, length);
[sourcecode language='python']
// get the number of char in the string
task strlen;
input [1024*8-1:0] str;
output [10:0] length;
reg [7:0] byte;
reg yes;
reg [10:0] i;
begin
length = 0;
i = 0;
get_byte(str, i, byte);
ischar(byte, yes);
while(yes&&(i<1024)) i =" i" length =" i;" style="font-weight:bold;">Calculate the length(length) of string(str) in verilog .
[/sourcecode]

Usage : strclr(str);

// clear string
task strclr;
output [1024*8-1:0] str;
reg [10:0] i;
begin
for(i = 0; i<1024; i =" i" style="font-weight:bold;">Copy the first numbers(length) of input string(str_in) to output string(str_out) in verilog.


Usage : strcpy(str_out, str_in, length);

// copy part of input string to output string
task strcpy;
output [1024*8-1:0] str_out;
input [1024*8-1:0] str_in;
input [9:0] length;
reg [10:0] str_length;
reg [10:0] i;
reg [7:0] byte;
reg [10:0] diff;
begin
strclr(str_out);
strlen(str_in, str_length);

if(length > str_length)
diff = 0;
else
diff = str_length - length;

for(i = str_length; i > diff; i = i - 1)
begin
get_byte(str_in, i-1, byte);
put_byte(str_out, i-1-diff, byte);
end
end
endtask

Cascade two input strings(str_1, str_2) to one output string(str_out)in verilog

Usage : strcat2(str_out, str_1, str_2);

// cascade two strings
task strcat2;
output [1024*8-1:0] str_out;
input [1024*8-1:0] str_1;
input [1024*8-1:0] str_2;
reg [10:0] str_1_length;
reg [10:0] str_2_length;
reg [10:0] str_3_length;
reg [10:0] length;
reg [9:0] index;
reg [7:0] byte;
begin
strclr(str_out);
strlen(str_1, str_1_length);
strlen(str_2, str_2_length);
str_3_length = str_1_length + str_2_length;
if( str_3_length > 1024 )
begin
$display("The length of cascade string is larger than 1024");
$display("%s", str_1);
$display("%s", str_2);
end
else
begin
for(length = str_1_length; length > 0; length = length -1)
begin
index = length - 1;
get_byte(str_1, index, byte);
put_byte(str_out, index+str_2_length, byte);
end
for(length = str_2_length; length > 0; length = length -1)
begin
index = length - 1;
get_byte(str_2, index, byte);
put_byte(str_out, index, byte);
end
end
end
endtask

cascade three input strings(str_1, str_2, str_3) to one output string(str_out)in verilog

Usage : strcat2(str_out, str_1, str_2, str_3 );


//Author : Jarod, jarod@benz.ee.nthu.edu.tw

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Learn Verilog in One Day

This is very simple and Easy Tutorial for Verilog Learn , With the help of this tutorial anyone can understand basics of verilog .

Comming Soon ....

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define vs parameter

there are two ways to define constants: the parameter, a constant that is local to a module and macro definitions, created using the `define compiler directive. A parameter, after it is declared, is referenced using the parameter name. A `define macro definition, after it is defined, is
referenced using the macro name with a preceding ` (back-tic) character. It is easy to distinguish between parameters and macros in a design because macros have a `identifier_name while a parameter is just the identifier_name without back-tic.

Parameters must be defined within module boundaries using the keyword parameter.
A parameter is a constant that is local to a module that can optionally be redefined on an instance-byinstance basis. For parameterized modules, one or more parameter declarations typically precede the port declarations in a Verilog-1995 style model, such as the simple register model in Example 1.

module register (q, d, clk, rst_n);
parameter SIZE=8;
output [SIZE-1:0] q;
input [SIZE-1:0] d;
input clk, rst_n;
reg [SIZE-1:0] q;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0; else q <= d;

endmodule

The Verilog-2001[5] version of the same model can
take advantage of both the ANSI-C style ports and module
header parameter list, as shown in Example 2.

module register2001

#(parameter SIZE=8)
(output reg [SIZE-1:0] q,
input [SIZE-1:0] d,
input clk, rst_n);
always @(posedge clk, negedge rst_n)
if (!rst_n) q <= 0; else q <= d;

endmodule

4. Parameters and Parameter Redefinition
When instantiating modules with parameters, in
Verilog-1995 there are two ways to change the parameters
for some or all of the instantiated modules; parameter
redefinition in the instantiation itself, or separate
defparam statements.
Verilog-2001 adds a third and superior method to
change the parameters on instantiated modules by using
named parameter passing in the instantiation itself (see
section 7).
5. Parameter redefinition using #
Parameter redefinition during instantiation of a module
uses the # character to indicate that the parameters of the
instantiated module are to be redefined.
In Example 3, two copies of the register from Example
1 are instantiated into the two_regs1 module. The SIZE
parameter for both instances is set to 16 by the #(16)
parameter redefinition values on the same lines as the
register instantiations themselves.

module two_regs1 (q, d, clk, rst_n);
output [15:0] q;
input [15:0] d;
input clk, rst_n;
wire [15:0] dx;
register #(16) r1 (.q(q), .d(dx),
.clk(clk), .rst_n(rst_n));
register #(16) r2(.q(dx), .d(d),
.clk(clk), .rst_n(rst_n));
endmodule

`define Inclusion
One popular technique to insure that a macro definition
exists before its usage is to use an `ifdef, or the new
Verilog-2001 `ifndef compiler directives to query for
the existence of a macro definition followed by either a
`define macro assignment or a `include of a file name
that contains the require macro definition.

`ifdef CYCLE
// do nothing (better to use `ifndef)
`else
`define CYCLE 100
`endif
`ifndef CYCLE
`include "definitions.vh"
`endif

The `undef compiler directive
Verilog has the `undef compiler directive to remove a
macro definition created with the `define compiler
directive.
Bergeron recommends avoiding the use of macro
definitions[11]. I agree with this recommendation.
Bergeron further recommends that all macro definitions
should be removed using `undef when no longer
needed[11]. I disagree with this recommendation. This
seems to be overkill to correct a problem that rarely exists.
Using the `define compiler directive to create global
macros where appropriate is very useful. Losing sleep
over the existence of global macro definitions and
tracking all of the `undef's in a design is not a good use
of time.
For the rare occasion where it might make sense to
redefine a macro, use `undef in the same file and at the
end of the file where the `define macro was defined.
Make sure that the last compiled macro definition is
likely to be the macro that you might want to access from
a testbench, because only one macro definition can exist
during runtime debug.
Again, using a `define-`undef pair should be
considered the last resort to a problem that could probably
be better handled using a better method.

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